Capacitive coupling mitigation for TSV-based 3D ICs
A Eghbal, PM Yaghini… - 2015 IEEE 33rd VLSI …, 2015 - ieeexplore.ieee.org
2015 IEEE 33rd VLSI Test Symposium (VTS), 2015•ieeexplore.ieee.org
TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the
circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a
TSV using circuit-level model is presented in this article. Two coding approaches are
proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any
given n× n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance.
The experimental results proves the efficacy of the proposed coding methods.
circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a
TSV using circuit-level model is presented in this article. Two coding approaches are
proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any
given n× n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance.
The experimental results proves the efficacy of the proposed coding methods.
TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n × n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.
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