In recent years, hardware accelerators based on field programmable gate arrays (FPGA) have been widely applied and the high-level synthesis (HLS) tools were created to facilitate the design of these accelerators. However, achieving high performance with HLS is still time-consuming and requires expert knowledge. Therefore, we present Chimera, an automated design space exploration tool for applying HLS optimization directives. It utilizes a novel multi-objective exploration method that seamlessly integrates active learning, evolutionary algorithm, and Thompson sampling, which enables it to find a set of optimized designs on a Pareto curve by only evaluating a small number of design points. On the Rosetta benchmark suite, Chimera explored design points that have the same or superior performance compared to highly optimized hand-tuned designs created by expert HLS users in less than 24 h. Moreover, it explores a Pareto frontier, where the elbow point can save up to 26% of flip-flop resource with negligible performance overhead.