The goal of this paper is to reduce the power and area of the Static Random Access Memory
(SRAM) array while maintaining the competitive performance. Here the various configuration
of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless
four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS
technologies. Then it is simulated using HSPICE to check for its functionality, Static Noise
Margin (SNM), power dissipation, area occupancy and access time. Except the precharge …

The goal of this paper is to reduce the power and area of the Static Random Access Memory
(SRAM) array while maintaining the competitive performance. Here the various configuration
of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless
fourtransistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS
technologies. Then it is simulated using HSPICE to check for its functionality, Static Noise
Margin (SNM), power dissipation, area occupancy and access time. Except the precharge …