Since the CMOS technology has reached to nanometer regime to meet the increasing demand of smarter and faster device, CMOS circuits have to face various short channel effects and variation in process parameters leading to degradation in performance and reliability. CMOS SRAM is one of the major circuits which degrades its performance due to short channel effects. To address this issue, in this paper, we proposed a novel static random-access memory cell with reduced leakage and improved stability using FinFET technology. In our design, we have shorted both the gates of the FinFET devices to apply a common biasing voltage. The cell is designed with FinFET logic, and results are compared with the conventional 6T FinFET cell in terms of leakage and stability at 22 nm technology node using HSPICE. The results show significant improvements in leakage and stability in comparison with the conventional SRAM cell and offer a good trade-off at sub-nanometer technology node.