Reducing the supply voltage in today′ s process technologies introduces significant
reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance
(CFT) techniques have been developed to ensure error free and performance efficient
execution in the presence of faults. A class of recent CFT techniques are based on the
concept of disabling cache portions, such as (sub-) blocks or words that include defective
bits, and reconfiguring operational ones (eg, physical or logical neighbor (sub-) blocks). All …