Fault tolerant CMOS logic using ternary gates
Y Berg, R Jensen, J Lomsdalen… - … on Multiple-Valued …, 2007 - ieeexplore.ieee.org
Y Berg, R Jensen, J Lomsdalen, H Gundersen, S Aunet
37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007•ieeexplore.ieee.orgIn this paper we present fault tolerant CMOS logic using redundancy and ternary signals.
The ternary gates are implemented using recharge logic which can be exploited in binary
and multiple-valued logic (MVL). Signals are processed through capacitors in such a way
that the logic operation of a gate is independent of the DC voltage applied on the inputs. By
combining signals through capacitors stuck on/stuck off and stuck at faults are not
destructive when redundancy is applied. Simulated data for 130 nm and 0.35 mum CMOS …
The ternary gates are implemented using recharge logic which can be exploited in binary
and multiple-valued logic (MVL). Signals are processed through capacitors in such a way
that the logic operation of a gate is independent of the DC voltage applied on the inputs. By
combining signals through capacitors stuck on/stuck off and stuck at faults are not
destructive when redundancy is applied. Simulated data for 130 nm and 0.35 mum CMOS …
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied. Simulated data for 130 nm and 0.35 mum CMOS processes are given.
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