… 1, the FinFET lacks the equivalent of a deep source/drain region that makes the formation
of low … with epitaxial raised source/drain (RSD) are shown to yield high performance FinFET …

… on the device performance as it plays a very … performance once through the reduction in
thermal conductivity (kth) of nanosheet channels and source/drain (S/D) regions due to increase …

… -FET for hole mobility enhancement, and Si1−yCy source/drain contributes lateral tensile
strain in the n-FET … wafer-level strain techniques for transistor performance enhancement, eg n-…

… – semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions
is … field due to an increase in junction depth between channel and source/drain, thereby …

… due to its reduced area, steeper SS, and higher ON-current in … of high performance Si/SiGe
heterojunction tunneling FETs … Toyoshima, “Source/drain engineering for sub-100 nm CMOS …

… silicide-to-source/drain regions increasingly limits transistor … the source/drain series resistance
will severely limit MOSFET … with historical improvement in high performance logic devices […

… source/drain in the scaling of traditional planar bulk MOSFET… of source/drain region with
raised source/drain technology would … For high performance (HP) design, the performances of …

… regions are slightly raised. Sourceldrain implantation and dopant … N-MOSFET comprising
Sic SO regions, metal gate and high-k gate dielectric was demonstrated. The SIC regions also …

… the gate and source/drain regions. Selective arsenic n+ and … into the elevated source/drain
and gate regions. This is … elevated source/drain device is suitable for highperformance …

… along with performance, power, and area perspectives [3]. … for FinFETs along with the
increase in ACCD alleviate the … Auth et al., “A 10nm high performance and low-power CMOS …