Hot Carrier Injection is one of the serious reliability issues of the NMOS transistors in the nanoscale regime. The effect of channel strain on hot carrier reliability of 45 nm strained Si/relaxed Si _1-x Ge _x CMOS and its impact in inverter and SRAM cell is presented in this paper. The introduction of the strain in the MOSFET boosts the impact ionization and hot carrier injection in the NMOS transistors. The existing hot carrier (HC) model of n-channel MOSFET is modified by incorporating mole fraction dependent impact ionization rate of strained Si MOSFET and the results are validated using TCAD simulations. The degradation of the inverter and SRAM cell due to HCI is analyzed using Cadence circuit simulator including the estimated threshold voltage variations in affected NMOS transistors. The 6T-SRAM cell and the inverter is designed using the strained CMOS technology. The effect of HC degradation in strained n-channel MOSFET on the static, read and write noise margins of the SRAM cell is analyzed. The noise margins which are improved by stronger pull down network designed with strained n-channel MOSFETs found to be degraded after the hot carrier stress. It is also observed that in strained CMOS inverter, the propagation delay is degraded due to HC injection in the higher rate than in the unstrained CMOS inverter.