We demonstrate record-high performance in normally-off single and multi-fin b-Ga 2 O 3
vertical power transistors. The effective channel mobility is significantly improved up to ~130 cm …

… High mobility is achieved by making devices with equivalent fixed oxide charge and surface
roughness compared to bulk. In this work, both the electron and hole mobility gains are …

There is a strong need for a large band gap pFET device with good performance for an efficient
high voltage CMOS platform for power conversion applications. In this work, we report on …

Two fully self-aligned via (SAV) integration schemes by metal recess approach and area-selective
dielectric-on-dielectric (DoD) method are reported in this paper. A topography with …

Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the
first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17…

… [32] developed an approach based on the concept of Büttiker probes [33], to treat the scattering
events in electronic devices. This approach is capable of capturing the essential physics …

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length,
enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high …

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs
with and without metal back gate (MBG) under sub-400C are proposed in this article. With …

… Tseng, "Device modeling of ferroelectric memory field-effect transistor for the application
of ferroelectric random access memory," IEEE Trans. Electron Devices, vol. 50, no. 1, pp. …

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate
transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-…