Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V
E Memisevic, J Svensson… - … IEEE International …, 2016 - ieeexplore.ieee.org
We present a vertical nanowire InAs/GaAsSb/GaSb TFET with a highly scaled InAs diameter
(20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for V ds = 0.1–…
(20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for V ds = 0.1–…
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
P Packan, S Akbar, M Armstrong… - … international electron …, 2009 - ieeexplore.ieee.org
A 32nm logic technology for high performance microprocessors is described. 2 nd generation
high-k + metal gate transistors provide record drive currents at the tightest gate pitch …
high-k + metal gate transistors provide record drive currents at the tightest gate pitch …
14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications
Z Krivokapic, U Rana, R Galatage… - … IEEE International …, 2017 - ieeexplore.ieee.org
Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art
14nm FinFET technology without any further process modification. Ferroelectric …
14nm FinFET technology without any further process modification. Ferroelectric …
SoC logic compatible multi-bit FeMFET weight cell for neuromorphic applications
We demonstrate an SoC logic compatible ferroelectric-metal field effect transistor (FeMFET)
digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with …
digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with …
A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications
SY Wu, CY Lin, MC Chiang, JJ Liaw… - … IEEE International …, 2016 - ieeexplore.ieee.org
For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications
is presented. This technology provides >3.3X routed gate density and 35%∼40% speed …
is presented. This technology provides >3.3X routed gate density and 35%∼40% speed …
Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity
YS Chen, HY Lee, PS Chen, PY Gu… - … IEEE International …, 2009 - ieeexplore.ieee.org
A 30×30 nm 2 HfO x resistance random access memory (RRAM) with excellent electrical
performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and …
performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and …
1Kbit FinFET Dielectric (FIND) RRAM in pure 16nm FinFET CMOS logic process
HW Pan, KP Huang, SY Chen, PC Peng… - … IEEE International …, 2015 - ieeexplore.ieee.org
A fully CMOS process compatible FinFET Dielectric RRAM (FIND RRAM) is firstly proposed
and demonstrated by 1kbit RRAM macro on 16nm standard FinFET CMOS logic platform. …
and demonstrated by 1kbit RRAM macro on 16nm standard FinFET CMOS logic platform. …
A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and …
C Auth, A Aliyarukunju, M Asoro… - … IEEE International …, 2017 - ieeexplore.ieee.org
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad
Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local …
Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local …
Ferroelectric HfZrOx Ge and GeSn PMOSFETs with Sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved Ids
We report the first ferroelectric (FE) HfZrO x (HZO) Ge and GeSn pMOSFETs with sub-60 mV/decade
subthreshold swing (SS) (40~43 mV/decade), negligible hysteresis, and enhanced …
subthreshold swing (SS) (40~43 mV/decade), negligible hysteresis, and enhanced …
A 40nm low-power logic compatible phase change memory technology
JY Wu, YS Chen, WS Khwa, SM Yu… - … IEEE International …, 2018 - ieeexplore.ieee.org
An embedded phase change memory technology in 40nm low-power logic platform is
demonstrated with minimal added process complexity - two non-critical additional masks over …
demonstrated with minimal added process complexity - two non-critical additional masks over …