Implement of a 10-bit 7.49 mW 1.2 GS/s DAC with a new segmentation method
In this paper, a new 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65
nm CMOS technology is presented. The new structure benefits from a combination of a
resistor ladder and current sources. By using the resistor ladder, the identical current
sources are weighted, which leads to remarkably reduce the number of current sources
needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-
free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL …
nm CMOS technology is presented. The new structure benefits from a combination of a
resistor ladder and current sources. By using the resistor ladder, the identical current
sources are weighted, which leads to remarkably reduce the number of current sources
needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-
free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL …
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