In this work, a detailed analysis of degradation and failure of semi-vertical GaN-on-Si trench MOSFETs is reported. OFF-state, semi-ON state and ON-state conditions were analyzed, to evaluate how the gate and drain bias can impact on the failure voltage. We demonstrate that: a) devices with a bilayer gate insulator (2.5 nm Al ₂ O ₃ interface dielectric to GaN, + 35 nm SiO ₂ main dielectric) have a superior performance, compared to single-insulator (35 nm Al ₂ O ₃ ) samples; b) in a drain step-stress, the gate voltage (resulting in different operating regimes, OFF, semi-ON or ON-state) can significantly impact on the failure voltage of the devices; c) stress at high V _GS and/or V _DS may induce a significant shift in threshold voltage, which is stronger when the devices are stressed in the ON-state. The results – complemented by 2D simulations – provide a description of the factors limiting the breakdown robustness of GaN vertical transistors.