Interface admittance measurement and simulation of dual gated CVD WS2 MOSCAPs: Mapping the DIT (E) profile
Abstract Dual gated 2ML WS 2 MOS Capacitors have been fabricated with capacitance
values as high as 2.7 uF/cm 2 (with single sheet charge centroid assumption for the WS 2
channel). Frequency and temperature dependent CV measurements were correlated with
simulations to extract the interface trap density-energy (D IT (E)) profile. We observe an
exponentially decaying defect distribution from the conduction band (EC) edge with a
magnitude of 8× 10 13 cm− 2 eV− 1 and an inverse slope of 0.12 eV and a similar …
values as high as 2.7 uF/cm 2 (with single sheet charge centroid assumption for the WS 2
channel). Frequency and temperature dependent CV measurements were correlated with
simulations to extract the interface trap density-energy (D IT (E)) profile. We observe an
exponentially decaying defect distribution from the conduction band (EC) edge with a
magnitude of 8× 10 13 cm− 2 eV− 1 and an inverse slope of 0.12 eV and a similar …
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