Speed and the overall performance of any digital signal processor are largely determined by
the efficiency of the multiplier units present within. The use of Vedic mathematics has
resulted in significant improvement in the performance of multiplier architectures used for
high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on
Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process
technology using Cadence EDA tool.

The need of low area and high speed Multiplier is increasing as the need of high speed
processors are needed. The multipliers used in Square and cube architecture have to be
more efficient in area and also in speed. In this paper a multiplier is implemented based on
UT and Nikhilam sutra which gives efficient results. The ripple carry adder in the multiplier
architecture increases the speed of addition of partial products. Comparison is made
between UT and Nikhilam sutra in terms of area (ie, No of 4-input LUT's and slices) and …