Low-latency pipelined crossbar arbitration
Heuristic, parallel, iterative matching algorithms for input-queued cell switches with virtual
output queuing require O (log N) iterations to achieve good performance. If the hardware
implementation of the number of iterations required is not feasible within the cell duration,
the matching process can be pipelined to obtain a matching in every cell time slot. However,
existing approaches incur a substantial latency penalty due to the way the pipelining is
performed, which renders them unattractive in latency-sensitive applications such as parallel …
output queuing require O (log N) iterations to achieve good performance. If the hardware
implementation of the number of iterations required is not feasible within the cell duration,
the matching process can be pipelined to obtain a matching in every cell time slot. However,
existing approaches incur a substantial latency penalty due to the way the pipelining is
performed, which renders them unattractive in latency-sensitive applications such as parallel …
[引用][C] Low-Latency Pipelined Crossbar Arbitration
M Cyriel - IEEE Communications Society Globecom 2004, 2004 - cir.nii.ac.jp
Low-Latency Pipelined Crossbar Arbitration | CiNii Research … Low-Latency Pipelined
Crossbar Arbitration …
Crossbar Arbitration …
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