… This paper offers a broad survey of techniques aimed at tackling latency in the literature up
… Internet latency reducing techniques, contrasting their gains in delay reduction versus the …

… Another drawback that is of special interest to us in this paper is the delay introduced in the
process of buffering (and interchanging) time slots because both the input and output frames …

… Our approach of simple universal parallel interconnections with high performance (… to
integrate large systems on a single wafer to reduce interconnect energy and latency. This …

… used to reduce the delay of long global interconnects [5]. … a new methodology for optimizing
global interconnect width which … chip edge and interconnect delay per unit length. Using this …

… to tailor the bandwidth and latency of the interconnect with the demands of the … process
level parallelism province of SMPs. In addition, due to the much lower communication latencies …

… to reduce resistance–capacitance delay of global interconnects [6]… interconnect width are
two key solutions to reduce the delay … , a novel methodology for optimizing global interconnects …

… This approach relies on the codesign of different network layers. (Section 3) • We propose a
symbol mapping technique that makes it possible to trade off higher bandwidth for lower BER…

… We analyzed various methods of RLC interconnect used currently and losses that take …
interconnects, hence interconnect delay has become few hundred times larger than transistor …

… to minimize the power-delay product. Simultaneously solving (16) and (18) for different on-chip
inductances and insertion points along the interconnect results in a power-delay product …

… The interconnect delay along one edge of a tile remains … as one approach to implementing
a chip-wide interconnection … reduce average communication latency by a factor of 1.3 to 1.6. …