… Impressive advancements in semiconductor process integration … The fin sidewall angle also
impacts the finFET performance … means, the fin cut has to be done after the isolation process, …

… fin width must be sublithographic, necessitating novel means … as pillars of semiconductor
surrounded by a gate, vertical … -etched trench for different etch techniques, post-etch treatments, …

… Wafers in a semiconductor manufacturing process are … process with atomic layer deposition
(ALD) technique. However, … both conditions concurrently for the duration of the etch process, …

… Fabrication process cf a FinFET (a) The fin is etched in SOI. (… the benefits of DG-CMOS for
performance [15-23]. A … fully depleted semiconductor would not provide means for adjusting …

… techniques and architectural designs of InAs-based FinFETs, … of the InAs-based semiconductor
surface to create a thin … is the RF-ID technology, which combines concurrent I–V and S-…

… for alternating Si fin lines beneath etched a-Si gates with a nominal … and will have an impact
on device electrical performance. All … Simultaneous migration of planar transistors to FinFET …

… enabling simultaneous area0scaling and circuit and variability … (a) FinFET process flow used
in TCAD process simulation … effectiveness of this method (Fig. 6a). A compressive stress in …

… -edge finFET nodes must cope with the complications of design concurrent with technology
… surrounding regions with techniques such as source/drain fin epitaxy and gate stress. The …

… use of semiconductor-based manufacturing methods in order … A FinFET is a non-planar
metal-oxide semiconductor (MOS) … of substrates can be concurrently involved in manufacturing, …

… planar double gate semiconductors, quasi-planar FinFET is … of given series, both lead to
the concurrent resistive loss. … We believe that employing the FinFET technique to improve …