As a crucial part of the Digital Signal Processor, a multiplier plays a major role in performing calculations within the processor. An important part of the electronic circuits in digital electronics is a binary multiplier which is capable of multiplying two binary digits. Most of the techniques developed for the purpose of multiplication involve calculation of the partial products separately and finally summing them to produce the multiplication output. This is the reason why a number of methods and technologies have been designed to make this multiplication process easier, minimizing the delay and error present. A comparative note on analysing CPL, Gate-Diffusion Input (GDI) and improved Shannon Adder technique is also made to determine the technique that uses minimum power when used as a full adder and GDI is found to be the optimum technique. This method uses CPL and Gate-Diffusion Input technique to implement an array multiplier and a modified Baugh-Wooley multiplier. However, a new Technique of improved Shannon Adder led to the implementation of the multipliers, resulting in better performance parameters. A comparative analysis on the power consumed and propagation delay is made with the help of Tanner EDA tool and it is found that Improved Shannon Adder implemented in modified Baugh-Wooley multiplier performs better than its peers.