In this paper, two low power and high-speed

27: 2 compressors proposed. The architectures are suitable for Implementation of parallel multipliers with operands meeting IEEE-754 standard cell based on ASIC design methodologies. Both designs are coded in VHDL language and implemented through commercially available EDA tool chain. The implementations give comparable results to full custom designs. In proposed architectures, 58.33% of carry-in/carryout wires are decreased. Furthermore, realistic simulations show critical path delay is 15.4% less than conventional architecture on 0.13 µm process technology1.