The leakage power consumption accounts for progressively huge portion of average power consumption in nanometer regime. To limit the power dissipation, different low-power techniques are suggested. This article presents the design and performance investigation of 6T carbon nano-tube field effect transistor (CNTFET) static random access memory (SRAM) cell design by using power reduction technique, i.e., sleep approach and proposed SBB approach for ultra-low-power applications at 32 nm technology. Power reduction techniques can play vital role in significant improvement of performance of 6T CNTFET SRAM cell. By incorporating power-gated technique, in 6T CNTFET SRAM cell design, 84.43%, 79.48%, and 60.92% improvement in average power dissipation is achieved for sleep approach, sleep with header switch, and sleep with footer switch, respectively. Similarly, in 6T CNTFET SRAM memory cell, leakage power minimization of 25.34%, 13.18%, and 3.37% is observed for sleep approach, sleep with header, and sleep with footer techniques, respectively. Performance analysis for proposed sleep body bias (SBB) 6T CNTFET SRAM cell design shows that proposed design has significant improvements in delay (53.48%), average power consumption (56.86%), power delay product (PDP) (80%), and leakage power dissipation (4%) in comparison to PG CNTFET SRAM and basic 6T CNTFET SRAM cell. Stability, of memory cells is also considered one of the most important parameters, is also examined utilizing butterfly curve method for proposed CNTFET SRAM cell.