For the design of complex digital signal processing systems, block diagram oriented synthesis of real time software for programmable target processors has become an important design aid. The synthesis approach discussed in this paper is based on multirate block diagrams with scalable synchronous dataflow (SSDF) semantics. For this class of dataflow graphs optimum vectorization techniques are introduced. Vectorization is treated as a transformation on an SSDF graph which increases the number of samples consumed or produced per activation of a block according to a specific optimization criterion. The presented optimization criterion jointly minimizes context-switching overhead caused by an activation of a block and maximizes the degree of vector processing of the important class of "single appearance minimum activation schedules" (SAMAS). This class comprises schedules in which each block appears exactly once and is activated minimum times. First, "single appearance" implies the most compact implementation of a schedule in terms of program memory. Second, "minimum activation" implies increased throughput according to optimum vectorization and minimal context-switching.< >