Parallelization of reversible ripple-carry adders
MK Thomsen, HB Axelsen - Parallel Processing Letters, 2009 - World Scientific
Parallel Processing Letters, 2009•World Scientific
The design of fast arithmetic logic circuits is an important research topic for reversible and
quantum computing. A special challenge in this setting is the computation of standard
arithmetical functions without the generation of garbage. Here, we present a novel
parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined
to form a reversible mk-bit ripple-block carry adder with logic depth for a minimal logic depth,
thus improving on the mk-bit ripple-carry adder logic depth. The underlying mechanisms of …
quantum computing. A special challenge in this setting is the computation of standard
arithmetical functions without the generation of garbage. Here, we present a novel
parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined
to form a reversible mk-bit ripple-block carry adder with logic depth for a minimal logic depth,
thus improving on the mk-bit ripple-carry adder logic depth. The underlying mechanisms of …
The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage.
Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth for a minimal logic depth , thus improving on the mk-bit ripple-carry adder logic depth . The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits.
We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.
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