Deep submicron technologies increase parameter variations, which will make microprocessor designs very difficult, since every variation requires a large safety margin for achieving specified timing yield. This means higher supply voltage, which results in large energy consumption. Razor flip-flop (FF) is a clever technique to eliminate the supply voltage margin by exploiting circuit-level timing speculation. It combines dynamic voltage scaling technique with the error detection and recovery mechanism. We are studying an alternative timing-error-predicting FF, named canary FF. This paper discusses a critical issue regarding the canary FF. Detailed gate- and architectural-level co-simulations unveil that canary FF occasionally misses predicting timing errors.