Real-time computing on multicore processors
Computer, 2016•ieeexplore.ieee.org
Architects of multicore chips for avionics must define and bound intercore interference,
which requires assuming a constant worst-case execution time for tasks executing on the
chip. With the Single Core Equivalent technology package, engineers can treat each core as
if it were a single-core chip.
which requires assuming a constant worst-case execution time for tasks executing on the
chip. With the Single Core Equivalent technology package, engineers can treat each core as
if it were a single-core chip.
Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.
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