Emerging wireless standards are continuously providing higher data rate and increased amount of flexibility. The recent trend in modern wireless transceivers is towards multistandard radio solutions that can support a varied range of wireless voice and data transfer services, and Software Defined Radios (SDR). In order to support multi-mode radio operation and switching between standards, reconfigurable hardware architectures have become essential. Moreover, the transceivers should be energy scalable so maximize battery life of the the hand-held radios. This necessitates analog-to-digital converters (ADCs) with reconfigurable bandwidth from 200 kHz up to 160 MHz and with up to 14-bits of resolution. Continuoustime delta-sigma (CT-∆ Σ) ADCs have recently been explored for wideband data conversion in wireless receivers due to much lower power consumption and inherent anti-alias filtering (AAF). Also, Delta-Sigma ADCs scale well with CMOS technology as they predominantly employ digital circuitry for achieving high dynamic range. Thus, a reconfigurable and digitally programmable CT-∆ Σ ADC is the logical choice for data conversion in multi-standard radios. We propose a digitally reconfigurable CT-∆ Σ ADC architecture with an ‘constant-capacitance scaled’loop-filter and programmable clocking to allow multi-standard operation. The proposed constant-C scaled CT-∆ Σ ADC employs a 4th order noise-shaping with a programmable multi-bit quantizer to achieve higher performance, improved stability and energy scalability. The loop filter is implemented using digitally programmable, feedforward compensated Active-RC integrators for high linearity and wider swing. The proposed architecture will enable design of ADC with digitally programmable conversion bandwidth from 312 kHz to 32 MHz with 40 modes.