Reducing test time via an optimal selection of LFSR feedback taps
A Afaq, A Al-Lawati - … of the Sixth International Symposium on …, 2001 - ieeexplore.ieee.org
Proceedings of the Sixth International Symposium on Signal …, 2001•ieeexplore.ieee.org
… The results of a simulation study demonstrate that in linear feedback shift register based
built-in VLSI testing, the selection of proper feedback taps can reduce the test application time
while retaining the testability goals. … Through a developed efficient algorithmic procedure
we computed every possible feedback taps leading to primitive characteristic polynomial in an
LFSR. Table 1 shows a list of such of connections with a minimum and a maximum possible
c, entry for 2 I n I 20. Since it is not possible to list such all entries and not relevant too …
built-in VLSI testing, the selection of proper feedback taps can reduce the test application time
while retaining the testability goals. … Through a developed efficient algorithmic procedure
we computed every possible feedback taps leading to primitive characteristic polynomial in an
LFSR. Table 1 shows a list of such of connections with a minimum and a maximum possible
c, entry for 2 I n I 20. Since it is not possible to list such all entries and not relevant too …
The results of a simulation study demonstrate that in linear feedback shift register-based built-in VLSI testing, the selection of proper feedback taps can reduce the test application time while retaining the testability goals.
ieeexplore.ieee.org
以上显示的是最相近的搜索结果。 查看全部搜索结果