The relentless push in technology scaling driven by Moore's Law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have taken advantage of the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique in dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction set architectures (ISAs). In this work, we demonstrate how the level of functional abstraction determines the capability and variety of a processor's functional units and accelerators thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, we propose a new functional instruction set architecture (F-ISA) that raises the level of functional abstraction of machine instructions. We show that by using this model in complement to existing architectures, a wider scope and diversity of functional units and accelerators is made available in order to take advantage of the ever increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution resulting in potentially substantial latency, memory footprint, and power performance gains.