SAD-based stereo matching circuit for FPGAs
2006 13th IEEE International Conference on Electronics, Circuits …, 2006•ieeexplore.ieee.org
… This paper proposes a new architecture that solves the matching problem on 8-bit
512x512 stereo images by using the SAD as similarity metric. The main innovation with
respect to the existing circuits cited above is the possibility of reducing the whole
computational time by exploiting operations common to different SAD computations. …
When compared to several existing FPGA-based and ASIC designs, the novel circuit
exhibits the highest frame rate and the lowest resources requirement. …
512x512 stereo images by using the SAD as similarity metric. The main innovation with
respect to the existing circuits cited above is the possibility of reducing the whole
computational time by exploiting operations common to different SAD computations. …
When compared to several existing FPGA-based and ASIC designs, the novel circuit
exhibits the highest frame rate and the lowest resources requirement. …
This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512times512 stereo images with a maximum disparity of 255. It achieves a 286 MHz running frequency and a frame rate of 25.6 f/s.
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