SRAM cell static noise margin and VMIN sensitivity to transistor degradation

AT Krishnan, V Reddy, D Aldrich… - 2006 International …, 2006 - ieeexplore.ieee.org
AT Krishnan, V Reddy, D Aldrich, J Raval, K Christensen, J Rosal, C O'Brien, R Khamankar…
2006 International Electron Devices Meeting, 2006ieeexplore.ieee.org
The SRAM cell sensitivity to transistor degradation is understood using a novel test
methodology. A new, semiempirical model that captures the observed trends is derived. The
key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/high
PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly from
the mean VTP shift which moves the overall distribution, and (c) NBTI-induced variance is
overwhelmed by the time-zero variation of the six transistors of the SRAM. These findings …
The SRAM cell sensitivity to transistor degradation is understood using a novel test methodology. A new, semiempirical model that captures the observed trends is derived. The key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/high PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly from the mean VTP shift which moves the overall distribution, and (c) NBTI-induced variance is overwhelmed by the time-zero variation of the six transistors of the SRAM. These findings enable a quantitative prediction that the NBTI-induced VMIN increase during burn-in is of the order of the NBTI-induced VT shift.
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