45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

SS Iyer, G Freeman, C Brodsky, AI Chou… - IBM Journal of …, 2011 - ieeexplore.ieee.org
… limit capacitance. A high-dose ion implantation process performed at close to vertical angles
into the trench opening has … Device and array co-design was critical for success. The access …

Dimension increase in metal-oxide-semiconductor memories and transistors

H Sunami - Advanced in Solid State Circuit Technologies. Rijeka …, 2010 - books.google.com
capacitance, he got an idea of a trench capacitor DRAM cell. … , highlydoped drain, and
silicon-on-insulator, respectively. Then, … to the vertical transistor, a few DRAM cells utilizing vertical

Silicon on Insulator Technology.

S Cristoloveanu - 1999 - books.google.com
… no need of wells or inter-device trenches. In addition, the vertical isolation achieves thin films,
… The SOI versatility has been taken advantage of for conceiving capacitor-less DRAMs. SOI …

[图书][B] Vertical 3D memory technologies

B Prince - 2014 - books.google.com
trench became the starting wafer for theconventional logic process. The DRAM capacitor still
has capacitance … be etched from bulk silicon or silicon-on-insulator (SOI) silicon. Schematic …

Performance characteristics of SOI DRAM for low-power application

JW Park, YG Kim, IK Kim, KC Park… - IEEE Journal of Solid …, 1999 - ieeexplore.ieee.org
… A 16-Mbit silicon-on-insulator (SOI) DRAM with a 0.3- m design … on process integration
of the cell capacitor using the pattern-… 2 and 3 show the vertical structure of the cross-sectional …

[图书][B] Fully depleted silicon-on-insulator: nanodevices, mechanisms and characterization

S Cristoloveanu - 2021 - books.google.com
devices, this book covers exhaustively the FD-SOI domain. Fully Depleted Silicon-On-Insulator
" For contributions to silicon-on-insulator technology and thin body devices." In the book, …

Perspectives on giga-bit scaled DRAM technology generation

K Kim - Microelectronics reliability, 2000 - Elsevier
… the more vertical profile of storage node, the larger capacitor … line capacitance of this novel
cell, COB stack cell, trench cell … is also eliminated by resembling nature of silicon-on-insulator (…

Surround gate transistor with epitaxially grown Si pillar and simulation study on soft error and rowhammer tolerance for DRAM

JW Han, J Kim, D Beery, KD Bozdag… - … on Electron Devices, 2021 - ieeexplore.ieee.org
… gate-all-around and vertical silicon pillar is examined in terms of … fabricated here is the cell
transistor before the cell capacitor … This fact was a key enabler of FDsilicon on insulator (SOI) …

Asymmetric and Double-Layered Gate-All-Around Structures of 1T-DRAM for Sensing Margin and Retention Improvement

S Kwon, I Yun - IEEE Transactions on Electron Devices, 2024 - ieeexplore.ieee.org
… memory (DRAM) is consisted of transistor and capacitor and … Structures, such as silicon-on-insulator,
double gate, or gate-… fabricated using the conventional vertical trench processes, …

Multifunction behavior of a vertical MOSFET with trench body structure and new erase mechanism for use in 1T-DRAM

JT Lin, PH Lin - IEEE Transactions on Electron Devices, 2014 - ieeexplore.ieee.org
… The capacitor is eliminated from the 1T1C-DRAM [8], and the … behaviors on a vertical
silicon-on-insulatorbased metal–… (a) 1T-DRAM cell array of the proposed device and disturbance …