The likelihood of soft errors increases with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit-cell area is condensed, single event upset that would have corrupted only a single bit-cell are now capable of upsetting multiple adjacent memory bit-cells per particle strike. Many of the errors occur when information is transmitted from one node to another node. Detection and correction of these errors is a must for many systems eg safety critical systems. To address this issue, a new approach is proposed in this paper to detect and correct multiple bit errors by using Horizontal-Vertical-Diagonal-Queen parity method (HVDQ). The experimental analysis shows the validation of the effectiveness of this approach by comparing its performance with existing approaches.