Submicrosecond latency video compression in a low-end FPGA-based system-on-chip
2018 28th International Conference on Field Programmable Logic and …, 2018•ieeexplore.ieee.org
In this paper, we present an efficient hardwareimplementation of a video encoder optimized
for ultra low-latency, using the Logarithmic Hop Encoding algorithm. This design provides
the following features:(i) A maximum marginal output latency of 23 clock cycles,(ii) small
area requirements,(iii) proven rate up to 95 Millions of pixels per second in a low-end FPGA
(ie FHD video can be streamed),(iv) on-the-fly configuration,(v) scalable architecture. The
proposed design has been tested in a real video transmission scenario, where the video …
for ultra low-latency, using the Logarithmic Hop Encoding algorithm. This design provides
the following features:(i) A maximum marginal output latency of 23 clock cycles,(ii) small
area requirements,(iii) proven rate up to 95 Millions of pixels per second in a low-end FPGA
(ie FHD video can be streamed),(iv) on-the-fly configuration,(v) scalable architecture. The
proposed design has been tested in a real video transmission scenario, where the video …
In this paper, we present an efficient hardwareimplementation of a video encoder optimized for ultra low-latency, using the Logarithmic Hop Encoding algorithm. This design provides the following features: (i) A maximum marginal output latency of 23 clock cycles, (ii) small area requirements, (iii) proven rate up to 95 Millions of pixels per second in a low-end FPGA (i.e. FHD video can be streamed), (iv) on-the-fly configuration, (v) scalable architecture. The proposed design has been tested in a real video transmission scenario, where the video transmitter prototype is implemented using a ZynqBerry board, leveraging all SoC capabilities.
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