Staggered ATPG with capture-per-cycle observation test points

Y Liu, J Rajski, SM Reddy, J Solecki… - … IEEE 36th VLSI Test …, 2018 - ieeexplore.ieee.org
… to reduce test application timecapture-per-cycle observation points to record data while
regular scan cells are still being loaded, and to generate more compact test patterns by utilizing

Logic BIST with capture-per-clock hybrid test points

E Moghaddam, N Mukherjee, J Rajski… - … on Computer-Aided …, 2018 - ieeexplore.ieee.org
… hybrid test point technology designed to reduce deterministic … by significantly reducing test
application time while preserving … the concept of capture-per-cycle observation test points. The …

Test point insertion for multi-cycle power-on self-test

S Wang, X Zhou, Y Higami, H Takahashi… - ACM Transactions on …, 2023 - dl.acm.org
… Unlike the production test, the POST requires reducing the test application time to meet the
indispensable test … Full-scan LBIST with capture-per-cycle hybrid test points. In Proc. Intl…

FF-Control point insertion (FF-CPI) to overcome the degradation of fault detection under multi-cycle test for POST

HT Al-Awadhi, T Aono, S Wang, Y Higami… - … on Information and …, 2020 - search.ieice.org
Test looks promising a way to reduce the test application … Degradation problem in multi-cycle
test. Based on the result of … Point Insertion technique (FF-CPI) to achieve the reduction of …

Capture-Pattern-Control to address the fault detection degradation problem of multi-cycle test in logic BIST

S Wang, T Aono, Y Higami, H Takahashi… - … IEEE 27th Asian Test …, 2018 - ieeexplore.ieee.org
capture-per-cycle hybrid-TPI technology by inserting some hybrid observation points to the
CUT (Circuit under Test… improving the test pattern reduction of multi-cycle test by enhancing …

Time and area optimized testing of automotive ICs

N Mukherjee, D Tille, M Sapati, Y Liu… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
… Finally, we address nontrivial processing challenges when fault simulating every … reduce
the simulation runtime. Recall (see Section II) that the capture-per-cycle observation test points

Test Compaction Using (k, 1)-Cycle Tests

I Pomeranz - 2024 IEEE 42nd VLSI Test Symposium (VTS), 2024 - ieeexplore.ieee.org
… required for applying the test set is reduced, even at the cost of increasing the number of …
To demonstrate this point, Figure 3 shows the numbers of (k, 1)-cycle tests with 0 ≤ k ≤ K …

[PDF][PDF] Field Test for Ensuring the Functional Safety of Automotive System

AHTM AL - ehime-u.repo.nii.ac.jp
… the two POST mentioned above application test strategies to … multi-cycle test to logic
built-in self-test scheme to reduce the … a DFT method named FF-Control Point Insertion (FF-CPI) …

On new class of test points and their applications

J Rajski, J Tyszer, J Zawada - 2018 IEEE International Test …, 2018 - ieeexplore.ieee.org
reduce deterministic pattern counts, improve test coverage, and reduce both ATPG run time
and test application time… Zawada, “Full-scan LBIST with capture-per-cycle hybrid test points,” …

Test time and area optimized BrST scheme for automotive ICs

N Mukherjee, D Tille, M Sapati, Y Liu… - … International Test …, 2019 - ieeexplore.ieee.org
… Finally, we address nontrivial processing challenges when trying to fault sim… reduce the
simulation runtime itself. Recall (see Section II) that the capture-per-cycle observation test points