The design of a low-power high-speed current comparator in 0.35-μm CMOS technology
S Ziabakhsh, H Alavi-Rad, M Alavi-Rad… - … on Quality Electronic …, 2009 - ieeexplore.ieee.org
S Ziabakhsh, H Alavi-Rad, M Alavi-Rad, M Mortazavi
2009 10th International Symposium on Quality Electronic Design, 2009•ieeexplore.ieee.orgA novel low power with high performance low current comparator is proposed in this paper
which comprises of low input impedance using a simple biasing method. It aimed for low
power consumption and high speed designs compared with other high speed designs. The
simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the
average power consumption is 130 muW for 100 nA input current at supply voltage of 1.8 V
using 0.35 micron CMOS technology.
which comprises of low input impedance using a simple biasing method. It aimed for low
power consumption and high speed designs compared with other high speed designs. The
simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the
average power consumption is 130 muW for 100 nA input current at supply voltage of 1.8 V
using 0.35 micron CMOS technology.
A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 muW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology.
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