The effects of memory-access ordering on multiple-issue uniprocessor performance

B Grayson, L John, C Chase - … IEEE International Performance …, 1999 - ieeexplore.ieee.org
… the effect of memory access ordering policies on processor pe$ormance. Relaxed ordering
… memory multiprocessor systems, even uniprocessor desktop computers are constrained by …

[PDF][PDF] The Effects of Memory-Access Ordering on Multiple-Issue Uniprocessor

B Grayson, L John, C Chase - researchgate.net
… We study the effect of memory access ordering policies on processor performance. Relaxed
… Our experiments confirm that memory access ordering plays a major role in superscalar …

[PDF][PDF] The Effects of Memory-Access Ordering on Multiple-Issue Uniprocessor Performance

BGLJC Chase - ai.mit.edu
… We study the effect of memory access ordering policies on processor performance. Relaxed
… Our experiments confirm that memory access ordering plays a major role in superscalar …

[PS][PS] The Effects of Memory-Access Ordering on Multiple-Issue Uniprocessor Performance Technical Report TR-PDS-1998-008

B Grayson, L John, C Chase - users.ece.utexas.edu
… We study the effect of memory access ordering policies on processor performance. Relaxed
… Our experiments confirm that memory access ordering plays a major role in superscalar …

Performance of database workloads on shared-memory systems with out-of-order processors

P Ranganathan, K Gharachorloo, SV Adve… - Proceedings of the …, 1998 - dl.acm.org
… -order execution and multiple issue in database applications, … cache-coherent non-uniform
memory access (CC-NUMA) … times for our base uniprocessor and multiprocessor systems. …

[PDF][PDF] The impact of architectural trends on operating system performance

M Rosenblum, E Bugnion, SA Herrod… - ACM SIGOPS …, 1995 - dl.acm.org
… years from now; (iii) we present results for both uniprocessor … comparing their relative
performance; and finally (iv) we present … memory access time shared memory. We use 1994 model …

The impact of instruction-level parallelism on multiprocessor performance and simulation methodology

VS Pai, P Ranganathan, SV Adve - … on High-Performance …, 1997 - ieeexplore.ieee.org
multiple issue, dynamic scheduling, and nonblocking reads. This paper presents the first
detailed analysis of the impact … required to fully exploit advances in uniprocessor technology for …

[PDF][PDF] Moola: Multicore cache simulator

CF Shelor, KM Kavi - 30th …, 2015 - computerscience.engineering.unt …
… The generation of a memory access trace file from a cycle … will not perform cycle accurate
timing of multiple-issue, out-of-order … This venerable cache simulator is limited to uniprocessor

Simultaneous multithreading: Maximizing on-chip parallelism

DM Tullsen, SJ Eggers, HM Levy - Proceedings of the 22nd annual …, 1995 - dl.acm.org
… -grain multithreaded processor, and single-chip, multiple-issue … high memory access demands,
meeting large forwarding … superscalar processors, we chose uniprocessor applications, …

[图书][B] Chip multiprocessor architecture: techniques to improve throughput and latency

OA Olukotun, L Hammond, JP Laudon - 2007 - books.google.com
… handle arbitration among independent memory access units. … techniques for accelerating
legacy uniprocessor code, more … such as parts and customer orders. Query 6 scans the largest …