at different growth temperatures on n-and p-type silicon substrates. The effect of processing
parameters and film thickness on the electrical quality of the oxide–semiconductor interface
was studied. Deep-level-transient spectroscopy and conductance-transient techniques
revealed 3–10× 10 11 cm− 2 eV− 1 interface trap densities, somewhat dependent on the
processing conditions. Charge trapping took place mainly between the semiconductor and …