Time-domain macromodels for VLSI interconnect analysis
SY Kim, N Gopal, LT Pillage - IEEE Transactions on Computer …, 1994 - ieeexplore.ieee.org
SY Kim, N Gopal, LT Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits …, 1994•ieeexplore.ieee.orgThis paper presents a method of obtaining time-domain macromodels of VLSI
interconnection networks for circuit simulation. The goal of this work is to include
interconnect parasitics in a circuit simulation as efficiently as possible, without significantly
compromising accuracy. Stability issues and enhancements to incorporate transmission line
interconnects are also discussed. A unified circuit simulation framework, incorporating
different classes of interconnects and based on the proposed macromodels, is described …
interconnection networks for circuit simulation. The goal of this work is to include
interconnect parasitics in a circuit simulation as efficiently as possible, without significantly
compromising accuracy. Stability issues and enhancements to incorporate transmission line
interconnects are also discussed. A unified circuit simulation framework, incorporating
different classes of interconnects and based on the proposed macromodels, is described …
This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects.< >
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