We consider techniques for translating quantum circuits between various architectures. Specifically, we are interested in generic techniques for translating a parallelized quantum circuit between two given architectures which give tight asymptotic bounds on the increase in circuit depth. We approach the problem using a graph-theoretic model for physical circuit architectures. The architectures considered include the complete graph Kn, the two-dimensional and three-dimensional square lattices, the cycle, and the graph of a line, which gives rise to the well-studied Linear Nearest Neighbour (LNN) circuit architecture model. We present results for translating circuits between these architectures, including a generic technique for translating circuits from arbitrary architectures to the LNN architecture.