In this paper, we investigate the gate misalignment effects in a 10-nm double-gate silicon-on-insulator MOSFET transistor with a 2-D Monte Carlo simulator. Quantum effects, which are of special relevance in such devices, are taken into account by using the multivalley effective conduction-band-edge method. Different gate misalignment configurations have been considered to study the impact on device performance, finding a current improvement when the gate misalignment increases the source–gate overlapping. Moreover, our results show that a 20% gate misalignment can be assumed for a drain current deviation smaller than 10%. Finally, the validity of the obtained results was assessed with a set of simulations for devices that have different gate lengths, silicon thicknesses, and oxide thicknesses.