The main idea in adaptive histogram equalization is to find the mapping for each pixel based on it local (neighborhood) gray scale distribution. In this method the contrast enhancement mapping applied to a particular pixel is a function of the intensity values of pixels immediately surrounding the pixel. Hence the number of times that this calculation should be repeated is the same as the number of pixels in the image. This gives rise to an extensive computation requirement, which even with some modifications cannot be used for real time image enhancement. So here another form of adaptive histogram equalization is used which is a compromise between global histogram equalization and fully adaptive histogram equalization - regional histogram equalization. The noise is also suppressed by contrast limited enhancement. The design is implemented in Field Programmable Gate Array (FPGA) which is known to be a better choice for hardware implementation where parallel processing algorithms such as image processing is carried out. The algorithm is successfully implemented in Xilinx Spartan 3AN on Altium Nanoboard NB3000 board using Altium Designer.