VeriGOOD-ML: An open-source flow for automated ML hardware synthesis
H Esmaeilzadeh, S Ghodrati, J Gu… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
This paper introduces VeriGOOD-ML, an automated methodology for generating Verilog
with no human in the loop, starting from a high-level description of a machine learning (ML)
algorithm in a standard format such as ONNX. The Verilog RTL is then translated through a
back-end design flow to GDSII, driven by a design planning approach that is well tailored to
the macro-intensive nature of ML platforms. VeriGOOD-ML uses three approaches to build
ML hardware: the TABLA platform uses a dataflow architecture that is well suited to non …
with no human in the loop, starting from a high-level description of a machine learning (ML)
algorithm in a standard format such as ONNX. The Verilog RTL is then translated through a
back-end design flow to GDSII, driven by a design planning approach that is well tailored to
the macro-intensive nature of ML platforms. VeriGOOD-ML uses three approaches to build
ML hardware: the TABLA platform uses a dataflow architecture that is well suited to non …
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