With multiple cores integrated on the same die, communication across cores is managed by on-chip interconnect called Network-on-Chip (NoC). Power and performance of these interconnect become a significant factor as the communication network has limitations of high network power consumption and delay. The buffers used in the NoC router consume a considerable amount of dynamic as well as static power. This paper attempts to reduce static power consumption by using Non-Volatile Memory technology based STT-RAM buffers. STT-RAM technology has the advantage of higher density and low leakage, but suffer from costly write operation, and weaker write endurance. These characteristics on whole impacts on the total network power consumption, network latency, and lifetime of the router. In this paper, we propose a compression technique at Network Interface, which is based on zero bytes present in data packets. We also propose a compression with the wear-leveling technique, which reduces the write variation in VCs to reduce uneven writes across the buffers.Experimental evaluation on full system simulator shows that proposed policy obtains 0.37 compression ratio and 63% reduction of total network flit. All these results in a significant decrease in total network power. The policies also show remarkable improvement in the lifetime with wear-leveling compression.