A 20 GHz sub-1V low noise amplifier and a resistive mixer in 90 nm CMOS technology
M Bao, H Jacobsson, L Aspemyr… - 2005 Asia-Pacific …, 2005 - ieeexplore.ieee.org
A 20 GHz sub-1 V low noise amplifier and a resistive mixer are designed and fabricated in
90 nm CMOS technology. The LNA achieves a good linearity along with a moderate gain …
90 nm CMOS technology. The LNA achieves a good linearity along with a moderate gain …
A 75.5-to-120.5-GHz, high-gain CMOS low-noise amplifier
DR Lu, YC Hsu, JC Kao, JJ Kuo… - 2012 IEEE/MTT-S …, 2012 - ieeexplore.ieee.org
In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is
proposed. A four-stage cascode configuration is adopted to achieve the high gain and …
proposed. A four-stage cascode configuration is adopted to achieve the high gain and …
Design of a 6GHz high-gain low noise amplifier
X Tang, F Huang, D Zhao - 2012 international conference on …, 2012 - ieeexplore.ieee.org
This paper presents the design of a low noise amplifier in 0.13-μm CMOS technology. The
conventional inductive degeneration is applied to reduce the noise figure. The amplifying …
conventional inductive degeneration is applied to reduce the noise figure. The amplifying …
A low power CMOS LNA for 1–10GHz application
MT Hsu, SY Hsu - 2009 Asia Pacific Microwave Conference, 2009 - ieeexplore.ieee.org
This paper presents a 1-10 GHz low power and low noise amplifier (LNA) with resistive-
feedback configuration. The design consists of two resistive-feedback amplifier. In order to …
feedback configuration. The design consists of two resistive-feedback amplifier. In order to …
A 24-GHz low power low noise amplifier using current reuse and body forward bias techniques in 0.18-µm CMOS technology
CC Kuo, H Wang - 2010 Asia-Pacific Microwave Conference, 2010 - ieeexplore.ieee.org
In this paper, a 24-GHz low noise amplifier (LNA) with low dc power in a standard 0.18 μm
CMOS technology is presented. The body forward bias and current reuse techniques are …
CMOS technology is presented. The body forward bias and current reuse techniques are …
A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology
A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-μm
CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum …
CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum …
1.5 V 5 GHz low noise amplifier with source degeneration
MT Hsu, TY Chih, GR Li - 2006 Asia-Pacific Microwave …, 2006 - ieeexplore.ieee.org
A 5GHz Low noise amplifier (LNA) has been implemented in a standard 0.18 um 1P6M
Mixed-Mode CMOS process. At 5GHz, this LNA provides about 10dB gain. Noise figure of …
Mixed-Mode CMOS process. At 5GHz, this LNA provides about 10dB gain. Noise figure of …
A 0.5–11 GHz CMOS low noise amplifier using dual-channel shunt technique
QT Lai, JF Mao - IEEE microwave and wireless components …, 2010 - ieeexplore.ieee.org
A 0.5-11 GHz CMOS low noise amplifier (LNA) is proposed, with a new dual-channel shunt
technique implemented, where one channel uses inductive-series peaking to provide flat …
technique implemented, where one channel uses inductive-series peaking to provide flat …
22 GHz amplifier using a 0.12 μm CMOS technology
D Pienkowski, G Boeck - 2006 International Conference on …, 2006 - ieeexplore.ieee.org
A 22 GHz low-noise amplifier (LNA) was designed, fabricated in standard 0.12 μm CMOS
technology and measured. The LNA chip achieves a maximum gain of 5.5 dB, a noise figure …
technology and measured. The LNA chip achieves a maximum gain of 5.5 dB, a noise figure …
24 GHz low-noise amplifier in 0.18 µm CMOS technology
KW Yu, YL Lu, D Huang, DC Chang, V Liang… - Electronics letters, 2003 - IET
A 24 GHz monolithic low-noise amplifier (LNA) is implemented in a standard 0.18 µm CMOS
technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 …
technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 …