In most phase locked loops, an obvious trade-off exists between settling time, output jitter
and power consumption. However, dependence of jitter on settling time is commonly …

A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

Phase-locked loops (PLLs) are widely used in various applications such as processors,
consumer electronics, and wireline communication systems. When digital circuits and a PLL …

This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It
aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known …

Noise generated in electronic devices greatly affects the performance of communication
systems. In oscillators, device baseband noise is up-converted to the RF region as phase …

Digital phase-locked loops (DPLLs) have recently emerged as a viable alternative to
classical charge-pump analog PLLs. By obviating the need for a large loop filter capacitor …

Phase-locked loops (PLLs) are widely used for clock generation in modern digital systems.
All-digital PLLs have been proposed to address design issues in conventional analog PLLs …

Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and
automatic bandwidth control. In Bang-Bang DPLLs assisted by DTC, performance is only li …

Analog Type-II phase-locked loops (PLLs) consume large area in loop-filter (LF) and employ
noisy and difficult-to-design charge-pump (CP). All-digital PLLs have strict jitter requirements …

This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed
scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock …