Crosstalk is generally recognized as a major problem in integrated circuit design. This paper
presents a novel approach to the efficient measurement of the effect of crosstalk on the delay …

This paper presents an approach to measurement of the effect of crosstalk on the delay of a
net using an algorithm whose worst-case complexity is quadratic to the number of nets. The …

Crosstalk is generally recognized as a major problem in IC design. This paper presents a
novel approach to the efficient measurement of the effect of crosstalk on the delay of a net …

2. Description of the Related Art The size, complexity, and operating or Switching speeds of
semiconductor ICs have increased, while feature geometries have decreased, and …

Digital circuits manufactured in deep sub-micron technologies may experience crosstalk
induced delay and noise signals. Crosstalk induced delay can be quite significant and …

In coupling delay computation, a Miller factor of more than 2/spl times/may be necessary to
account for active coupling capacitance when modeling the delay of deep submicron …

Methods are presented for generating bounds on interconnection delays in a combinational
network having specified timing requirements at its input and output terminals. An automatic …

Deep submicron effects, along with increasing interconnect densities, have increased the
complexity of the routing problem. Whereas previously we could focus on minimizing …

We show how to incorporate global static timing constraints into global routing. Our
approach is based on the min-max resource sharing model that proved successful for global …

In the past, the dominant approach to solving timing problems in layout was based on
sorting logical paths according to their criticality and assigning of different weights to nets …