In this work, HfSiON gate dielectric is integrated for the first time in dual gate oxide of DRAM
with recess channel arrary transistor (RCAT) and W/poly-Si gate for the development of sub …

Conventional self-aligned MOSFET transistors with poly-silicon gate-electrode were
successfully fabricated using Hf-oxide and Zr-oxide as high-k gate-dielectrics. The gate …

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its
double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and …

We demonstrate for the first time the performance of aggressively scaled triple gate devices
with a MOCVD TiN/HfO gate stack. The transistors have physical gate lengths down to 40 …

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide
thickness (EOT) HfO/sub 2/gate dielectric is demonstrated. The excellent thermal stability of …

This paper describes the limitations and challenges involved in designing gigabit DRAM
chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage …

The first stacked DRAM (dynamic RAM) cell using vertical ultra-thin SOI (silicon-on-insulator)
MOSFET (DELTA, or fully depleted lean-channel transistor) is proposed. Since the ultra-thin …

In this paper, we report for the first time Ge MOS characteristics with ultra thin rapid thermal
CVD HfO/sub 2/gate dielectrics and TaN gate electrode. Using the newly developed pre …

We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/gate
dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single …

MOSFETs with high quality ultra thin (EOT/spl sim/10.3/spl Aring/) HfO/sub 2/gate stacks and
self-aligned dual poly-Si gate are fabricated and characterized. Both n-and p-MOSFETs …