In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is
proposed. A four-stage cascode configuration is adopted to achieve the high gain and …

This paper presents a W-band low power, wideband low noise amplifier design in 65nm
CMOS. Low noise amplifier consists of six-stage to obtain high gain. For a high-data rate …

This paper presents the design of a low noise amplifier in 0.13-μm CMOS technology. The
conventional inductive degeneration is applied to reduce the noise figure. The amplifying …

This paper presents a 60-GHz high-gain, low-power, 3.7-dB noise-figure (NF), CMOS low-
noise amplifier (LNA) fabricated with a 90-nm process. The CMOS LNA exhibited a two …

A 20 GHz sub-1 V low noise amplifier and a resistive mixer are designed and fabricated in
90 nm CMOS technology. The LNA achieves a good linearity along with a moderate gain …

A 60 GHz low-noise amplifier (LNA) implemented in a 65 nm CMOS process is presented.
Due to the use of a gain-boosted input stage and binary controlled attenuators, the LNA …

A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-μm
CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum …

A 0.5-11 GHz CMOS low noise amplifier (LNA) is proposed, with a new dual-channel shunt
technique implemented, where one channel uses inductive-series peaking to provide flat …

A low-power and wide-band 63GHz CMOS low-noise amplifier (LNA) with a single-ended
input and differential outputs is proposed. To realize low power consumption, single-ended …

30 GHz low noise amplifier was designed and fabricated in a 90nm digital CMOS process.
The mm-wave amplifier has a peak gain of 20 dB at 28.5 GHz and a 3dB bandwidth of 2.6 …