A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its
double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and …

Experimental measurements and 2-D device simulation are used to investigate a
capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are …

A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates
and thin body reduce off state leakage and. disturb problems. Dopant fluctuations, which can …

We review the current status of the 1T-DRAM development, illustrate how this concept can
be extended to fully depleted (FD) SOI, and demonstrate a first circuit application. A memory …

A 4Mb DRAM with cross point trench transistor cell Page 1 [See page 369 for Figure 3. J
SESSION XIX: DYNAMIC RAMS FAM 19.5: A 4Mb DRAM with Cross-point Trench Transistor …

This paper describes the limitations and challenges involved in designing gigabit DRAM
chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage …

This paper describes a 256 Mb DRAM chip architecture which provides up to/spl times/32
wide organization. In order to minimize the die size, three new techniques: an exchangeable …

This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM,
and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less …

An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate
high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed …

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for
file applications are described. The newly proposed and developed circuits are a self …