This paper describes the limitations and challenges involved in designing gigabit DRAM
chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage …

A modern, comprehensive introduction to DRAM for students and practicing chip designers
Dynamic Random Access Memory (DRAM) technology has been one of the greatestdriving …

Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS
DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage …

Many challenges emerge as the DRAM enters into a generation of the gigabit density era.
Most of the challenges come from the shrink technology which scales down minimum …

This DRAM architecture optimization, which appears transparent to the memory controller,
significantly reduces power consumption. With trivial additional logic, using the posted-CAS …

In this paper, a 0.15/spl mu/m embedded DRAM technology is described which provides a
cost-effective means of delivering high bandwidth, low power consumption, noise immunity …

The state of the art in megabit dynamic random access memory (DRAM) circuit and chip
design is reviewed in terms of essential design parameters such as signal-to-noise ratio …

An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate
high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed …

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high
performance, while retaining the density advantage of the one-transistor DRAM cell. The …

Discusses improvement of current device jitter budget. A DRAM incorporating these
improvements is expected to operate with 1.3 Gb/s/pin signaling rate (650MHz clock rate) …