Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

Y Shin, J Seomun, KM Choi, T Sakurai - ACM Transactions on Design …, 2010 - dl.acm.org
Power Gating has become one of the most widely used circuit design techniques for
reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI …

Semicustom design methodology of power gated circuits for low leakage applications

HO Kim, Y Shin - IEEE Transactions on Circuits and Systems II …, 2007 - ieeexplore.ieee.org
The application of power gating to cell-based semi-custom design typically calls for
customized cell libraries, which incurs substantial engineering efforts. In this brief, a …

[图书][B] Logic synthesis for low power VLSI designs

S Iman, M Pedram - 2012 - books.google.com
Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive
treatment of power modeling and optimization at the logic level. More precisely, this book …

Synthesis of active-mode power-gating circuits

J Seomun, I Shin, Y Shin - IEEE Transactions on Computer …, 2012 - ieeexplore.ieee.org
Active leakage is transient, which can be suppressed by design techniques such as dual-Vt.
Active-mode power-gating (AMPG) can further reduce active leakage by power-gating …

[PDF][PDF] Trends in low-power VLSI design

T Darwish, M Bayoumi - The Electrical Engineering Handbook, 2005 - academia.edu
As advances in lithography and fabrication of the N-type metal oxide superconductor
(NMOS) technology became possible in the 1970s, the bipolar digital logic, transistor …

[PDF][PDF] Design technologies for low power VLSI

M Pedram - Encyclopedia of Computer Science and Technology, 1997 - mpedram.com
Low power has emerged as a principal theme in today's electronics industry. The need for
low power has caused a major paradigm shift where power dissipation has become as …

On gate level power optimization using dual-supply voltages

C Chen, A Srivastava… - IEEE Transactions on Very …, 2001 - ieeexplore.ieee.org
In this paper, we present an approach for applying two supply voltages to optimize power in
CMOS digital circuits under the timing constraints. Given a technology-mapped network, we …

Experimental measurement of a novel power gating structure with intermediate power saving mode

S Kim, SV Kosonocky, DR Knebel… - Proceedings of the 2004 …, 2004 - dl.acm.org
A novel power gating structure is proposed for low-power, high-performance VLSI. This
power gating structure supports an intermediate power saving mode as well as a traditional …

[PDF][PDF] Strategies & methodologies for low power VLSI designs: A review

K Kaur, A Noor - International Journal of Advances in Engineering & …, 2011 - academia.edu
Low power has emerged as a principal theme in today's world of electronics industries.
Power dissipation has become an important consideration as performance and area for …

[图书][B] Low-power VLSI circuits and systems

A Pal - 2014 - books.google.com
The book provides a comprehensive coverage of different aspects of low power circuit
synthesis at various levels of design hierarchy; starting from the layout level to the system …